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HV7131GP
CMOS Image Sensor with Image Signal Processing
HV7131GP
V2.4
2004/10/29 V2.4
1
HV7131GP
Revision History
Revision V1.0 V1.1 Script Date 2001/11/08/Thu - 2001/11/14/Thu 2001/12/21/Fri Comments - HV7131GP Preliminary is released - Gamma slope table of Knee/De-Knee is added, and some misprints are corrected V1.2 2002/03/25/Mon - Knee/De-Knee function is abandoned, instead 10bit ADC is implemented. - Register descriptions are revised - Frame timing is revised. V1.3 V1.4 V1.5 2002/04/25/Thu 2002/05/06/Mon 2002/05/13/Tue - register information is updated - Data output timing & interface is added Chip layout information is revised, and
miscellaneous typo errors are corrected V1.6 2002/05/28/Tue chip layout information and power is omitted for
confidentiality,
consumption
information is added. V1.7 V1.8 V1.9 V2.0 V2.1 V2.2 V2.3 2002/06/14/Fri 2002/12/26/Thu. 2003/01/17/Fri. 2003/06/04/Wed. 2003/07/10/Thu.. 2003/12/11/Thu.. 2004/06/26/Sat - CLCC 40 Pin Diagram added - PKG Drawing Added - Register Description Revision - 40 pin diagram revision - ENB Setting guide information is added - C[7:0] PAD information is added. -I2C Data Hold Time Revision - External pull-up/ pull-down resistance is added V2.4 2004/10/29/Fri - Value of SNR, Dynamic Range, Sensitivity is added at Features.
Copyright by MagnaChip Semiconductor Ltd., all right reserved 2001, 2002, 2003, 2004
Disclaimer
This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd., assumes no responsibility or liability arising from use of circuit described, and no patent licenses are implied.
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HV7131GP
CONTENTS
General Description................................................................................................................................. 4 Features .................................................................................................................................................... 4 Block Diagram.......................................................................................................................................... 5 Pin Diagram .............................................................................................................................................. 7 Pin Description......................................................................................................................................... 7 Functional Description............................................................................................................................ 9 Pixel Architecture......................................................................................................................... 9 ENB Setting guide information for normal stand-by mode .......................................................... 9 Sensor Imaging Operation........................................................................................................... 9 10bit on-chip ADC ..................................................................................................................... 10 Gamma Correction .................................................................................................................... 10 Color Interpolation ..................................................................................................................... 11 Color Correction & Color Space Conversion............................................................................. 12 Digital Gain Control ................................................................................................................... 12 Output Formatting...................................................................................................................... 12 Auto Exposure Control .............................................................................................................. 12 Auto White Balance ................................................................................................................... 13 Spectral Characteristics............................................................................................................. 13 Register Description.............................................................................................................................. 13 Frame Timing........................................................................................................................................... 45 Anti-Banding Configuration...................................................................................................................... 50 Data Output Timing and Interface ........................................................................................................ 51 Output Data Format ...............................................................................................................................51 Bayer Data Format................................................................................................................................... 53 I2C Chip Interface .................................................................................................................................. 54 AC/DC Characteristics .......................................................................................................................... 55 Electro-Optical Characteristics ............................................................................................................ 59 CLCC Package Specification ................................................................................................. 60
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HV7131GP
General Description
HV7131GP is a highly integrated single chip CMOS color image sensor implemented by proprietary MagnaChip 0.35um CMOS sensor process realizing high sensitivity and wide dynamic range. Total pixel array size is 652x492, and 652x488 pixels are active. Each active pixel composed of 4 transistors has a micro-lens to enhance sensitivity, and converts photon energy to analog pixel voltage. On-chip 10bit Analog to Digital Converter (ADC) digitizes analog pixel voltage, and on-chip Correlated Double Sampling (CDS) scheme reduces Fixed Pattern Noise (FPN) dramatically. General image processing functions such as gamma correction, color interpolation, color correction, color space conversion, auto exposure, and auto white balance are implemented to diversify its applications, and various output formats are supported for the sensor to easily interface with different video codec chips. The integration of sensor function and image processing functions make HV7131GP especially very suitable for mobile imaging systems such as IMT-2000 phone's video part that requires very low power and system compactness.
Features
1/4 inch optical format Total pixel : 652 x 492 / Active pixel : 652x488 5.6um x 5.6um active square pixel Micro-lens for high sensitivity RGB mosaic color filter array On-chip 10 bit ADC Correlated double sampling for reduction of Fixed Pattern Noise Black Level Compensation Gamma correction by programmable piecewise linear approximation 3x3 Color interpolation Color correction by programmable 3x3 matrix operation Color space conversion from RGB to YCbCr Sub-sampling Modes : 1/4, 1/16 Various output formats : YCbCr 4:2:2, YCbCr 4:4:4, RGB 4:4:4, Bayer 8bit / 16bit Data Bus Mode Automatic Exposure Control Automatic White Balance Control Frame Rate : 30 f/s at 25Mhz, HBLANK = 208, VBLANK = 8 Power Consumption: 86mW @ 30f/s and 2.8V, 68mW @ 15f/s and 2.8V, 336uW @ power down Operation Voltage Range : 2.6V ~ 3.0V, Operation Temperature : -10 ~ +50 degrees Celsius
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HV7131GP
Package Types : CLCC 40 PIN, COB(Chip-on-Board), COF(Chip-on-Flex) * To the matter concerning package, Wafer business companies are unrelated contents. Dynamic Range : 52 dB SNRMAX : 42 dB Sensitivity : 3000 mV / lux sec (Green Pixel)
Block Diagram
RESETB MCLK ENB SCK SDA Timing Control Config Registers I2C Slave Test Logic
Row Decoder
Pixel Array 652 x 492
Column CDS 10bit ADC
PGA RGB Gain
Auto White Balance
Auto Exposure Control
Gamma
Color Interpolation
Color Correction & Color Space Conversion
YCbCr Digital Gain Control
Output Formatting
VCLK Y[7:0] C[7:0] VSYNC HSYNC
1. 2.
PGA : Programmable Gain Amplifier Color Correction and Color Space Conversion are merged into one matrix operation for hardware simplification
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HV7131GP
Pixel Array Structure
Metal Shielded Black Level Array [2 line] G B R G G B R G .... .... GG BG R G G B R G
G B
R G
G B
R G
.... ....
GG BG
R G
G B
R G
Metal Shielded Black Level Array [2 line]
Note: If black level data output is enabled(SCTRC[1] set to high) with Bayer mode set(SCTRA[1:0] == 2'b00), data output in the areas of Metal Shielded Black Level Array can be monitored during 4 line period of HSYNC right after VSYNC goes from high state to low state.
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Pin Diagram
DGNDI 4 DVDDI 5 C[0] 3 C[1] 2 C[2] 1 C[3] C[4] C[5] C[6] C[7] 35 DVDDC 34 DGNDC 33 AGND
40 39 38 37 36
NC 6 Y[7] 7 Y[6] 8 Y[5] 9 Y[4] 10 Y[3] 11 Y[2] 12 Y[1] 13 Y[0] 14 DGNDC 15
HV7131GP HV7131GP CLCC 40 PIN
CLCC 40 PIN Top View Top View
32 AVDD 31 ENB 30 RESETB 29 STROBE 28 AGND 27 AVDD 26 NC
16 17 18 19 20 21 22 23 24 25 DVDDC DGNDI MCLK VCLK HSYNC VSYNC SDA SCK DGNDI DVDDI
* To the matter concerning package, Wafer business companies are unrelated contents.
Pin Description
The input mode of HSYNC/VSYNC/Y[7:0]/C[7:0] is used to test internal image processing function in mass production so that it should be not assumed about slave mode operation. The device does not support slave mode operation. When 8bit output mode is used, we recommend that C[7:0] be set up as pull-up or pull-down according to I2C regulation. Although there is no pull-up or pull-down, it is no influence on function operation and leakage current does not become a problem after stabilization of chip. In case of application with C[7:0] without pull-up or pull-down, any problems were not generated.
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HV7131GP
Pin 1-3 4 5 6 7-14 15 16 17 18 19 20
Type B G P N O G P G I O O
Symbol C[2:0] DGNDI DVDDI NC Y[7:0] DGNDC DVDDC DGNDI MCLK VCLK HSYNC
Description Video Chrominance Data[2:0] Digital Ground for I/O Buffer Digital Power for I/O Buffer No Connection Video Luminance Data[7:0] Ground for Internal Digital Block Power for Internal Digital Block Digital Ground for I/O Buffer Master Input Clock Video Output Clock Video Horizontal Line Synchronization signal. Image data is valid, when HSYNC is high.
21
O
VSYNC
Video Frame Synchronization signal. VSYNC is active at start of image data frame.
22 23 24 25 26 27 28 29 30 31
B I G P N P G O I I
SDA SCK DGNDI DVDDI NC AVDD AGND STROBE RESETB ENB
I2C Standard data I/O port I2C Clock Input Digital Ground for I/O Buffer Digital Power for I/O Buffer No Connection Power for Analog Block Ground for Analog Block Strobe Signal Output Sensor Reset, Low Active Sensor sleep mode is controlled externally by this pin when sleep mode register bit SCTRB[4] is low. ENB low : sleep mode, ENB high : normal mode
32 33 34 35 36-40
P G G P B
AVDD AGND DGNDC DVDDC C[7:3]
Power for Analog Block Ground for Analog Block Ground for Internal Digital Block Power for Internal Digital Block Video Chrominance Data[7:3]
* To the matter concerning package, Wafer business companies are unrelated contents. Note) B: bi-direction pin, P: power pin, G: ground pin, O: output pin, I: Input pin
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HV7131GP
Functional Description
Pixel Architecture
Pixel architecture is a 4 transistor NMOS pixel design. The additional use of a dedicated transfer transistor in the architecture reduces most of reset level noise so that fixed pattern noise is not visible. Furthermore, micro-lens is placed upon each pixel in order to increase fill factor so that high pixel sensitivity is achieved.
ENB Setting guide information for normal stand-by mode
It is necessary that this kind of initialization sequence for the normal stand-by mode of HV7131GP after system power on
System power On More than 4cycle Sensor operation sequence Sensor Power down sequence
DVDD/AVDD
RESETB
Low 1[ms] or more
MCLK
Low 1'st VSYNC out
VSYNC
Low 2.0 [Mcycle] for 1'st VSYNC out
ENB
Low 2.086 [Mcycle] for logic stable time 1ms
I2C Video stream Don't care Initialization sequence Don't care Camera Mode
ex) If MCLK = 25[Mhz] => 2.086[Mcycle] / 25[MHz] = 83.44 ms The time period of ENB high value have to keep for 83.44[ms] or more
Sensor Imaging Operation
Imaging operation is implemented by the offset mechanism of integration domain and scan domain(rolling shutter scheme). First integration plane is initiated, and after the programmed integration time is elapsed, scan plane is initiated, then image data start being produced.
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Time
Integration Plane Frame 0 Scan Integration Plane Frame 1 Scan Plane Frame 1 Frame 1 Time Plane Frame 0 Frame 0 Time Integration Time
10bit on-chip ADC
On-chip ADC converts analog pixel voltage to 10bit digital data.
Gamma Correction
Piecewise linear gamma approximation method is implemented. Ten piece linear segments are supported and user-programmable. Gamma Slope Registers are programmed as the integer value of real slope value that is multiplied by 64.
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Out Start 9 : : Start 3 Start 2 Slope 1 Start 1 Slope 0 Start 0 0 4 16 32 64 128 192 256 512 768 1023 In
Gamma Transfer Function Color Interpolation
Three methods are supported to interpolate missing R, G, or B for mosaic image data from pixel array as follows. a) 3x3 linear color interpolation Interpolation is done by moving 3x3 interpolation window by one pixel horizontally and vertically b) 1/4 subsampling color interpolation Interpolation is done by moving 2x2 interpolation window by two pixels each time horizontally and vertically. The equation for color interpolation in each 2x2 window is simple as follows.
R = R1 G = (G1 + G2)/2 B = B1
R1 G2
G1 R B1 G B
c) 1/16 subsampling color interpolation
R1 G2 R G
G1 B1
R G R2 G4
G
1/16
B
R G
B
G B
G3 B2
R = (R1 + R2)/2 G = (G1 + G2 + G3 + G4)/4 B = (B1 + B2)/2
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Color Correction & Color Space Conversion
Both of Color Correction and Color Space conversion are implemented by 3x3 matrix operation, so that two stages may be merged into one matrix stage. Color correction matrix may be resolved by measuring sensor's color spread characteristics for primary color source and calculating the inverse matrix of color spread matrix. For color space conversion matrix, the equation from CCIR-601 standard is normally used. Therefore, the intended single matrix for color correction and color space conversion may be resolved as below. Intended single matrix = Color Space Conversion Matrix * Color Correction Matrix Intended single matrix coefficients are programmable from -127/64 to 127/64. Programming register value for intended single matrix coefficients should be resolved by the following equations. For positive values, CMAxx = Integer (Real Coefficient Value x 64); For negative values, CMAxx = Two Complement(Integer (Real Coefficient Value x 64)); Real Coefficient Value values from -127/64 to 127/64 can be programmed.
CCIR-601 YCbCr color space conversion equation < Conversion Equation > Y = (77R + 150G + 29B)/256 Range: 16 ~ 235 Cb = (-44R -87G + 131B)/256 + 128 Range: 16 ~ 240 Cr = (131R - 110G - 21B)/256 + 128 Range: 16 ~ 240 < Reverse Conversion > R = Y + 1.371(Cr - 128) G = Y - 0.698(Cr - 128) - 0.336(Cb - 128) B = Y + 1.732(Cb - 128) In the above equations, R, G, and B are gamma-corrected values.
Digital Gain Control
Y, Cb, and Cr digital channels are scaled by this block that receives scaling values from Auto Exposure and Auto White Balance blocks. Scaling resolution is 1/128 and value range is 1.9 ~ 0.1.
Output Formatting
The output formats such as Bayer Raw Data, RGB 4:4:4, YCbCr 4:4:4, and YCbCr 4:2:2 are supported. Possible output bus widths are 8 bits and 16bits, and the sequence of Cb and Cr are programmable.
Auto Exposure Control
Y mean value is continuously calculated every frame, and the integration time value is increased or decreased according to difference between target Y mean value and current frame Y mean value.
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HV7131GP
Auto White Balance
Cb/Cr frame mean value is calculated every frame and according to Cb/Cr frame mean values' displacement from Cb/Cr white target point, R/B scaling values for R/B data are resolved.
Spectral Characteristics
S pe c tral R e s pon s e 1.4 1.2 1 Relative Sensitivity 0.8 0.6 0.4 0.2 0 400 B G R
450
500
550 W av e le n gth (n m)
600
650
700
Register Description
Register Symbol Address (Hex) Device ID Sensor Control A Sensor Control B Sensor Control C Row Start Address High Row Start Address Low Column Start Address High Column Start Address Low Window Height High Window Height Low DEVID SCTRA SCTRB SCTRC RSAH RSAL CSAH CSAL WIHH WIHL 00 01 02 03 08 09 0a 0b 0c 0d Default (Hex) 40 0b 00 01 00 02 00 02 01 e0 Product ID, Revision No. Operation mode, X/Y flip, Image size Power down, Clock division Sensor Internal control Register Row Start Address[8] Row Start Address[7:0] Column Start Address[9:8] Column Start Address[7:0] Window Height Address[8] Window Height Address[7:0] Description
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HV7131GP
Window Width High Window Width Low HBLANK Time High HBLANK Time Low VBLANK Time High VBLANK Time Low Red Color Gain Green Color Gain Blue Color Gain Preamp Gain Preamp Gain Min Preamp Gain Max Preamp Gain Nominal ASP Bias Reset Clamp ADC Bias Red Pixel Black Offset
WIWH WIWL HBLANKH HBLANKL VBLANKH VBLANKL RCG GCG BCG PREAMP PREMIN PREMAX PRENOM ASPBIAS RSTCLMP ADCBIAS OREDI
0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 20 21
02 80 00 d0 00 08 10 10 10 10 00 3f 10 13 07 0f 7f
Window Width Address[9:8] Window Width Address[7:0] HBLANK Time [15:8] HBLANK Time [7:0] VBLANK Time [15:8] VBLANK Time [7:0] Gain for Red Pixel Output Gain for Green Pixel Output Gain for Blue Pixel Output Preamp Gain for Pixel Output Preamp Gain Min Value for AE Preamp Gain Max Value for AE Preamp Gain Normal Value for AE Amp Bias, Pixel Bias Reset Level Clamping Value ADC Bias ADC Offset Value for Light-shielded Red Pixel ADC Offset Value for Light-shielded Green
Green Pixel Black Offset
OGRNI
22
7f Pixel ADC Offset Value for Light-shielded Blue
Blue Pixel Black Offset Red Pixel Active Offset Green Pixel Active Offset Blue Pixel Active Offset Black Level Threshold ISP Function Enable ISP Output Format ISP Output Polarity Green Edge Threshold
OBLUI OREDU OGRNU OBLUU BLCTH ISPFEN OUTFMT OUTINV EDGETH
23 24 25 26 27 30 31 32 33
7f Pixel RO RO RO ff 0f 39 00 00 ADC Offset Value for Active Red Pixel ADC Offset Value for Active Green Pixel ADC Offset Value for Active Blue Pixel Black Level Threshold Value Image processing functions enable Image data output format control Output signal polarity control Green pixel edge threshold for 3x3 color interpolation
Color Matrix Coefficient 11 Color Matrix Coefficient 12 Color Matrix Coefficient 13 Color Matrix Coefficient 21
CMA11 CMA12 CMA13 CMA21
34 35 36 37
2e c5 0c 0d
Color matrix coefficient 11 Color matrix coefficient 12 Color matrix coefficient 13 Color matrix coefficient 21
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HV7131GP
Color Matrix Coefficient 22 Color Matrix Coefficient 23 Color Matrix Coefficient 31 Color Matrix Coefficient 32 Color Matrix Coefficient 33 Gamma Segment Point 0 Gamma Segment Point 1 Gamma Segment Point 2 Gamma Segment Point 3 Gamma Segment Point 4 Gamma Segment Point 5 Gamma Segment Point 6 Gamma Segment Point 7 Gamma Segment Point 8 Gamma Segment Point 9 Gamma Segment Slope 0 Gamma Segment Slope 1 Gamma Segment Slope 2 Gamma Segment Slope 3 Gamma Segment Slope 4 Gamma Segment Slope 5 Gamma Segment Slope 6 Gamma Segment Slope 7 Gamma Segment Slope 8 Gamma Segment Slope 9 AE Mode 1 AE Mode 2 Integration Time High Integration Time Middle Integration Time Low AE Target AE Lock & Fine
CMA22 CMA23 CMA31 CMA32 CMA33 GMAP0 GMAP1 GMAP2 GMAP3 GMAP4 GMAP5 GMAP6 GMAP7 GMAP8 GMAP9 GMAS0 GMAS1 GMAS2 GMAS3 GMAS4 GMAS5 GMAS6 GMAS7 GMAS8 GMAS9 AEM1 AEM2 INTH INTM INTL AETGT
38 39 3a 3b 3c 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 63 64 65 66 67
3c f7 f8 cf 39 00 04 1c 34 54 78 90 a4 e0 f4 40 80 60 40 24 18 14 0f 05 02 39 ba 07 a1 20 70 a2
Color matrix coefficient 22 Color matrix coefficient 23 Color matrix coefficient 31 Color matrix coefficient 32 Color matrix coefficient 33 Start point for gamma line segment 0 Start point for gamma line segment 1 Start point for gamma line segment 2 Start point for gamma line segment 3 Start point for gamma line segment 4 Start point for gamma line segment 5 Start point for gamma line segment 6 Start point for gamma line segment 7 Start point for gamma line segment 8 Start point for gamma line segment 9 Slope value for gamma line segment 0 Slope value for gamma line segment 1 Slope value for gamma line segment 2 Slope value for gamma line segment 3 Slope value for gamma line segment 4 Slope value for gamma line segment 5 Slope value for gamma line segment 6 Slope value for gamma line segment 7 Slope value for gamma line segment 8 Slope value for gamma line segment 9 Auto exposure mode selection 1 Auto exposure mode selection 2 Integration Time [23:16] Integration Time [15:8] Integration Time [7:0] Frame Luminance Target Value Y frame mean value displacement
Tune AELBND
Boundary
boundary from AE target where AE goes into Lock state. Fine tuning boundary is also specified.
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HV7131GP
AE Unlock Boundary
AEUNLCK
68
2a
Y frame mean value displacement from AE target where AE update speed transits from 2x integration unit speed to 1x integration unit speed
AE Integration Step High AE Integration Step Middle AE Integration Step Low AE Integration Limit High AE Integration Limit Middle AE Integration Limit Low AWB Mode 1 AWB Mode 2 Cb Target
AEINCH AEINCM AEINCL AELMH AELMM AELML AWBM1 AWBM2 CBTGT
6a 6b 6c 6d 6e 6f 70 71 73
1 e8 48 17 d7 84 41 2 80
Integration Increment Step Unit [17:16] Integration Increment Step Unit [15:8] Integration Increment Step Unit [7:0] Integration Time Limit [23:16] Integration Time Limit [15:8] Integration Time Limit [7:0]] AWB mode selection 1 AWB mode selection 2 Cb Plane Target Frame Mean Value. Normal white point is 80h.
Cr Target
CRTGT
74
80
Cr Plane Target Frame Mean Value. Normal white point is 80h.
AWB Lock Boundary
AWBLB
75
2
Cb/Cr Frame Mean Displacement from Cb Target and Cr Target where AWB goes into LOCK state
AWB Unlock Boundary
AWBULB
76
06
Displacement from ideal white pixel where AWB release from LOCK state
AWB White Pixel Boundary
AWBWPB
77
30
Displacement from ideal white pixel where AWB recognizes a pixel as a white pixel affected by light source
Y Digital Gain
YGAIN
78
40
Y digital gain for Auto Exposure Control
Cb Digital Gain
CBGAIN
79
40
Cb digital gain for Auto White Balance control
Cr Digital Gain
CRGAIN
7a
40
Cr digital gain for Auto White Balance control
AE Status AWB Status Y Frame Mean
AEST AWBST YFMEAN
7b 7c 7d
RO RO RO
AE operation status AWB operation status Y Frame Mean Value
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Cb Frame Mean Cr Frame Mean Minimum Anti-Banding Gain
CBFMEAN CRFMEAN BNDGMIN
7e 7f 80
RO RO 08
Cb Frame Mean Value Cr Frame Mean Value Minimum gain value with Anti-Banding enabled
Maximum Gain
Anti-Banding BNDGMAX
81
18
Maximum gain value with Anti-Banding enabled
Integration-Scan Offset High Integration-Scan Offset Middle Integration-Scan Offset Low AWB Luminance
Plane
ISOFSH
82
RO
Integration-Scan Plane Offset[23:16]
Plane
ISOFSM
83
RO
Integration-Scan Plane Offset[16:8]
Plane
ISOFSL
84
RO
Integration-Scan Plane Offset[7:0]
High AWBLUHI
8a
C8
During CbCr frame mean value calculation, AWB discards pixel of which luminance is larger than this register value.
Boundary
AWB
Luminance
Low AWBLULO
8b
0a
During CbCr frame mean value calculation, AWB discards pixel of which luminance is smaller than this register value.
Boundary
AWB Valid Number
AWBNO
8c
02
AWB update when the number of valid color pixel is larger than (this minimum value x 64)
Dark
Bad
Pixel DPCMODE
90
0
Dark
Bad
Pixel
Concealment
Mode
Concealment Mode Dark Bad Integration Time High DPCINTH 91 13
selection Integration Time Value High Byte where filtering operation gets active when dark bad pixel filtering mode is enabled.
Dark Bad Integration Time Middle
DPCINTM
92
12
Integration Time Value Middle Byte where filtering operation gets active when dark bad pixel filtering mode is enabled.
Dark Bad Integration Time Low
DPCINTL
93
D0
Integration Time Value Low Byte where filtering operation gets active when dark bad pixel filtering mode is enabled.
Dark Bad G Threshold
DPCGTH
94
0c
Neighbor-differential threshold value that specify G dark bad pixel
Dark Bad R/B Threshold
DPCCTH
95
0c
Neighbor-differential threshold value that specify R/B dark bad pixel
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Device ID [DEVID : 00h : 40h]
7 6 5 4 3 2 1 0
Product ID 0 1 0 0 0
Revision Number 0 0 0
High nibble represents Sensor Array Resolution, Low Nibble represents Revision Number.
Sensor Control A [SCTRA : 01h : 0bh]
7 6 5 4 3 2 1 0
Operation Mode 0 0 0 0
X-Flip 1
Y-Flip 0
Video Mode 1 1
Category
Operation Mode 1111
Note At CDS operation, reset and image bit-lines are all written to high. This mode is just for monitoring purpose.
1110 TestC 1101
At CDS operation, image bit-line is written to high. In this mode, all Bayer data output are 8'h00. At CDS operation, reset bit-line is written to high. In this mode, all Bayer data output are 8'hff.
1100 10x1 TestA 10x0
Reserved ADC overflow test with CDS output disconnected. In this mode, all Bayer data output are 8'hff. ADC underflow test with CDS output disconnected. In this mode, all Bayer data output are 8'h00.
TestI TestB Normal
011x 0101 0100 0000
Image processing function test I2C state machine test Sensor operation state machine test Normal imaging operation
X-Flip Y-Flip Video Mode
Image is horizontally flipped Image is vertically flipped 11 10 01 00 3x3 color interpolation 1/4 subsampling mode 1/16 subsampling mode Bayer output mode
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Sensor Control B [SCTRB : 02h : 00h]
7 6 5 4 3 2 1 0
AE/AWB Block Sleep 0
Datapath Block Sleep 0
Analog Block Sleep 0
Sleep Mode
Strobe Enable
Clock Division
0
0
0
0
0
< Clock Acronym Definition > MCF : Master Clock Frequency SCF : Sensor Clock Frequency VCF : Video Clock Frequency < Clock Frequency Relation > MCF : MCF SCF : DCF/2 DCF : MCF/Clock Division ICF SCF for 3x3 interpolation, DCF : Divided Clock Frequency ICF : Image Processing Clock Frequency LCF : Line Clock Frequency
SCF/2 for 1/4 subsampling mode SCF/4 for 1/16 subsampling mode VCF : ICF for 16bit output, ICF*2 for 8bit output LCF : 1/(HBLANK Period + HSYNC Period)
AE/AWB Block Sleep Datapath Block Sleep
AE/AWB block goes into sleep mode with this bit set to high. Image processing datapath block goes into sleep mode with this bit set to high.
Analog Block Sleep
all internal analog block goes into sleep mode with this bit set to high. With All Digital Block Sleep active, sensor goes into power down mode.
Sleep Mode Strobe Enable
all internal digital and analog block goes into sleep with this bit set to high. When strobe signal is enabled by this bit, STROBE pin will indicates when strobe light should be splashed in the dark environment to get adequate lighted image.
Clock Division
divides input master clock(IMC) for internal use. Internal divided clock frequency(DCF) is defined as master clock frequency(MCF) divided by specified clock divisor. Internal divided clock frequency(DCF) is as follows. 000 : MCF, 100 : MCF/16, 001 : MCF/2, 101 : MCF/32, 010 : MCF/4, 110 : MCF/64, 011 : MCF/8 111 : MCF/128
Sensor Control C [SCTRC : 03h : 01h]
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7
6
5
4
3
2
1
0
Black Level Average Output
Y[7:0] Pad Output with HSYNC high
C[7:0] Pad Output with 8bit mode
HSYNC in VBLANK
reserved
Unified Gain
Black Level Data Enable
Black Level Compensation
0
0
0
0
0
0
0
1
Black Level Average Output
This bit enable R/G/B Active Offset registers[24h-26h] to represent black level average value, instead of updated active offset values
Y[7:0] Pad Output with With this bit set to high, Y[7:0] pads go into tri-state when HSYNC is HSYNC high inactive.
C[7:0] Pad Output with With this bit set to high, C[7:0] pads go into zero driving state with 8bit 8bit mode HSYNC in VBLANK output mode enabled. Otherwise, these pads go into tri-state. VBLANK is equivalent to VSYNC, and HSYNC is the inversion of HBLANK, and this bit control whether HSYNC is active or not when VBLANK unit is LCF.
VSYNC (VBLANK) HSYNC
Unified Gain Black Level Data Enable Black Level Compensation
G gain is used for R, G, and B analog gain HSYNC is generated for light-shielded pixels in 4 lines.
Black level average values of light-shielded pixels are compensated when active image data is produced.
Row Start Address High [RSAH : 08h : 0h]
7 6 5 4 3 2 1 0
reserved
Row Start Address High
0
0
0
0
0
0
0
0
Row Start Address Low [RSAL : 09h : 02h]
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HV7131GP
7
6
5
4
3
2
1
0
Row Start Address Low 0 0 0 0 0 0 1 0
Row Start Address register defines the row start address of image read out operation.
Column Start Address High [CSAH : 0ah : 0h]
7 6 5 4 3 2 1 0
reserved
Column Start Address High
0
0
0
0
0
0
0
0
Column Start Address Low [CSAL : 0bh : 02h]
7 6 5 4 3 2 1 0
Column Start Address Low 0 0 0 0 0 0 1 0
Column Start Address register defines the column start address of image read out operation.
Window Height High [WIHH : 0ch : 1h]
7 6 5 4 3 2 1 0
reserved
Window Height High
0
0
0
0
0
0
0
1
Window Height Low [WIHL : 0dh : e0h]
7 6 5 4 3 2 1 0
Window Height Low 1 1 1 0 0 0 0 0
Window Height register defines the height of image to be read out.
Window Width High [WIWH : 0eh : 2h]
7 6 5 4 3 2 1 0
reserved 0 0 0 0 0 0
Window Width High 1 0
Window Width Low [WIWL : 0fh : 80h]
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7
6
5
4
3
2
1
0
Window Width Low 1 0 0 0 0 0 0 0
Window Width Address register defines the width of image to be read out.
HBLANK Time High [HBLANKH : 10h : 00h]
7 6 5 4 3 2 1 0
HBLANK Time High 0 0 0 0 0 0 0 0
HBLANK Time Low [HBLANKL : 11h : d0h]
7 6 5 4 3 2 1 0
HBLANK Time Low 1 1 0 1 0 0 0 0
HBLANK Time register defines data blank time between current line and next line by using Sensor Clock Period unit (1/SCF), and should be larger than 208(d0h).
VBLANK Time High[VBLANK : 12h : 00h]
7 6 5 4 3 2 1 0
VBLANK Time High 0 0 0 0 0 0 0 0
VBLANK Time Low[VBLANK : 13h : 08h]
7 6 5 4 3 2 1 0
VBLANK Time Low 0 0 0 0 1 0 0 0
VBLANK Time register defines active high duration of VSYNC output. Active high VSYNC indicates frame boundary between continuous frames. For VSYNC-HSYNC timing relation in the frame transition, please refer to Frame Timing section.
Each sensor has a little different photo-diode characteristics so that the sensor provides internal adjustment registers that calibrate internal sensing circuit in order to get optimal performance. Sensor characteristics adjustment registers are as below.
R Color Gain [RCG : 14h : 10h]
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7
6
5
4
3
2
1
0
reserved 0 0 0 1
R Color Gain 0 0 0 0
G Color Gain [GCG : 15h : 10h]
7 6 5 4 3 2 1 0
reserved 0 0 0 1
G Color Gain 0 0 0 0
B Color Gain [BCG : 16h : 10h]
7 6 5 4 3 2 1 0
reserved 0 0 0 1
B Color Gain 0 0 0 0
There are three color gain registers for R, G, B pixels, respectively. Programmable range is from 0.5X ~ 2.5X. Effective Gain = 0.5 + B<5:0>/32. These registers may be used for white balance and color effect with independent R,G,B color control. Default gain is 1X.
Preamp Gain [PREAMP : 17h : 10h]
7 6 5 4 3 2 1 0
Preamp Gain 0 0 0 1 0 0 0 0 Preamp Gain is common gain for R, G, B channel and used for auto exposure control. Programmable range is from 0.5X ~ 16.5X. Default gain is 1.5X. Gain = 0.5 + B<7:0>/16
Preamp Gain Min [PREMIN : 18h : 00h]
7 6 5 4 3 2 1 0
Preamp Gain Min 0 0 0 0 0 0 0 0
Preamp Gain Min is minimum value of preamp gain when sensor adjusts pre-amplifier gain for auto exposure control. Programmable range is same as preamp gain. Recommended value is 0.5X.
Preamp Gain Max [PREMAX : 19h : 3fh]
7 6 5 4 3 2 1 0
Preamp Gain Max 0 0 1 1 1 1 1 1
Preamp Gain Max is maximum value of preamp gain when sensor adjusts preamp gain for auto
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exposure control. Programmable range is same as preamp gain. Recommended value is 16.5X.
Preamp Gain Normal [PRENOR : 1ah : 10h]
7 6 5 4 3 2 1 0
Preamp Gain Normal 0 0 0 1 0 0 0 0
Preamp Gain Normal is reference value of preamp gain when sensor adjusts preamp gain for auto exposure control. First, sensor controls integration time before adjusting preamp gain for auto exposure control. After integration time is changed to the minimum or maximum value, sensor adjusts preamp gain from this register value. Refer to figure of AE mode1 register(60H). Programmable range is same as preamp gain. Recommended value is 1.5X.
ASP Bias [ASPBIAS : 1bh : 13h]
7 6 5 4 3 2 1 0
reserved 0 0
Pixel Bias
Amp Bias 1 0 0 1 1
0
controls the amount of current in internal pixel bias circuit to amplify pixel Pixel Bias output effectively. The larger register value increases the amount of current. controls the amount of current in internal amplifier bias circuit to amplify Amplifier Bias pixel output effectively. The larger register value increases the amount of current.
Reset Level Clamp [RSTCLMP : 1ch : 07h]
7 6 5 4 3 2 1 0
Reserved 0 0 0 0 0
Reset Level Clamp 1 1 1
Because extremely bright image like sun affects reset data voltage of pixel to lower, bright image is captured as black image in image sensor regardless of correlated double sampling. To solve this extraordinary phenomenon, we adopt the method to clamp reset data voltage. Reset Level Clamp controls the reset data voltage to prevent inversion of extremely bright image. The larger register value clamps the reset data level at highest voltage level. Default value is 7 to clamp the reset data level at appropriate voltage level.
ADC Bias [ADCBIAS : 20h : 0fh]
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7
6
5
4
3
2
1
0
Reserved 0 0 0 0 1 1
ADC Bias 1 1
ADC Bias controls the amount of current in ADC bias circuit to operate ADC effectively. The larger register value increases the amount of current.
Red Pixel Black Offset [OREDI : 21h : 7fh]
7 6 5 4 3 2 1 0
Red Pixel Black Offset 0 1 1 1 1 1 1 1
Green Pixel Black Offset [OGRNI : 22h : 7fh]
7 6 5 4 3 2 1 0
Green Pixel Black Offset 0 1 1 1 1 1 1 1
Blue Pixel Black Offset [OBLUI : 23h : 7fh]
7 6 5 4 3 2 1 0
Blue Pixel Black Offset 0 1 1 1 1 1 1 1
These registers control the offset voltage of ADC that changes the black level value for light-shielded pixels, red, green and blue pixel respectively. Register bit functions are composed as follows.
Pixel Black Offset[7]
The bit specifies whether to subtract or add offset voltage in ADC input for light-shielded pixels.
Pixel Black Offset[6:0] This value specifies the amount of offset voltage for light-shielded pixels.
Red Pixel Active Offset [OREDU : 24h : RO]
7 6 5 4 3 2 1 0
Red Pixel Active Offset RO RO RO RO RO RO RO RO
Green Pixel Active Offset [OGRNU : 25h : RO]
7 6 5 4 3 2 1 0
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Green Pixel Active Offset RO RO RO RO RO RO RO RO
Blue Pixel Active Offset [OBLUU : 26h : RO]
7 6 5 4 3 2 1 0
Blue Pixel Active Offset RO RO RO RO RO RO RO RO
These registers control the offset voltage of ADC that changes the black level value for active pixels, red, green and blue pixel respectively. The registers are internally updated by black level compensation logic, and are read-only registers. Register bit functions are composed as follows.
Pixel Active Offset[7]
The bit specifies whether to subtract or add offset voltage in ADC input for active pixels.
Pixel Active Offset[6:0] This value specifies the amount of offset voltage for active pixels.
Black Level Threshold [BLCTH : 27h : ffh]
7 6 5 4 3 2 1 0
Black Level Threshold 1 1 1 1 1 1 1 1
The register specifies the maximum value which determines whether light-shielded pixel output is valid. When light-shielded pixel output exceeds this limit, the pixel is not accounted for black level calculation.
ISP Function Enable [ISPFEN : 30h : 0fh]
7 6 Reserved 5 4 3 Matrix Operation 2 Color Interpolation 1 Gamma Correction 0 reserved
0
0
0
0
1
1
1
1
In HV7131GP, two matrix operations of color correction & color space Matrix Conversion conversion are merged into one matrix operation. With this bit set to high, the matrix operation is enabled, and otherwise R/G/B data is output through output formatter. Color Interpolation With SCTRA[1:0] set to 3x3 color interpolation, this bit control the final channel between color interpolated R/G/B and Bayer data. With this bit set
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to low, R/G/B channels for one pixel are fed with the same one Bayer value so that image similar to black & white is produced. Gamma Correction With this bit set to high, 10 segments piecewise approximate gamma is enabled.
Output Format [OUTFMT : 31h : 39h]
7 6 5 4 3 2 1 0
Gammacorrected Bayer
Bayer 8bit output
Cb First
Y First
8 Bit Output
reserved
YCbCr 4:4:4
YCbCr 4:2:2
0
0
1
1
1
0
0
1
Gamma-corrected Bayer Bayer 8bit output
Bayer data that are gamma corrected is output when Bayer mode is set in SCTRA register. Bayer data is output with 8bit mode. two LSB of 10 bit Bayer data is stripped out.
Cb First Y First
Cb pixel in front of Cr pixel in 16bit or 8bit video data output modes Y pixel in front of Cb and Cr pixels in 8bit video output mode. This option is meaningful only with 8bit output mode.
8 Bit Output YCbCr 4:4:4
Image Data is produced only in Y[7:0]. C[7:0] should be discarded YCbCr 24bit data for a pixel is produced with 16bit output mode. With color space conversion disabled, RGB 24bit data for a pixel is produced in this mode. This mode is meaningful only with 16bit output mode.
YCbCr 4:2:2
YCbCr data for a pixel is produced with 8/16 output mode
Output Inversion[OUTINV : 32h : 0h]
7 6 5 4 3 2 1 0
reserved
Clocked HSYNC
VSYNC inversion
HSYNC inversion
VCLK inversion
0
0
0
0
0
0
0
0
Clocked HSYNC
In HSYNC, VCLK is embedded, that is, HSYNC is toggling at VCLK rate during normal HSYNC time
VSYNC inversion HSYNC inversion
VSYNC output polarity is inverted HSYNC output polarity is inverted
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VCLK inversion
VCLK output polarity is inverted
Green Edge Threshold[EDGETH : 33h : 00h]
7 6 5 4 3 2 1 0
Green Edge Threshold
0
0
0
0
0
0
0
0
In 3x3 color interpolation mode, missing G pixel is interpolated with edge detection considering neighbor G pixels, and this register controls edge threshold to select edge direction. The smaller value means that the more patterns are recognized as edge, and image may get sharper, but not always.
Color Matrix Coefficients Both of Color Correction and Color Space conversion are implemented by 3x3 matrix operation, so that two stages may be merged into one matrix stage. Color correction matrix may be resolved by measuring sensor's color spread characteristics for primary color source and calculating the inverse matrix of color spread matrix. For color space conversion matrix, the equation from CCIR-601 standard is normally used. Therefore, the intended single matrix for color correction and color space conversion may be resolved as below. Intended single matrix = Color Space Conversion Matrix * Color Correction Matrix Intended single matrix coefficients are programmable from -127/64 to 127/64. Programming register value for intended single matrix coefficients should be resolved by the following equations. For positive values, CMAxx = Integer(RealCoefficientValue x 64); For negative values, CMAxx = TwoComplement(Integer(RealCoefficientValue x 64)); RealCoefficientValue values from -127/64 to 127/64 can be programmed.
CCIR-601 YCbCr color space conversion equation < Conversion Equation > Y = (77R + 150G + 29B)/256 Range: 16 ~ 235 Cb = (-44R -87G + 131B)/256 + 128 Range: 16 ~ 240 Cr = (131R - 110G - 21B)/256 + 128 Range: 16 ~ 240 < Reverse Conversion > R = Y + 1.371(Cr - 128) G = Y - 0.698(Cr - 128) - 0.336(Cb - 128) B = Y + 1.732(Cb - 128) In the above equations, R, G, and B are gamma-corrected values
Color Matrix Coefficient 11 [CMA11 : 34h : 2eh]
7 6 5 4 3 2 1 0
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Color Matrix Coefficient 11 0 0 1 0 1 1 1 0
Color Matrix Coefficient 12 [CMA12 : 35h : c5h]
7 6 5 4 3 2 1 0
Color Matrix Coefficient 12 1 1 0 0 0 1 0 1
Color Matrix Coefficient 13 [CMA13 : 36h : 0ch]
7 6 5 4 3 2 1 0
Color Matrix Coefficient 13 0 0 0 0 1 1 0 0
Color Matrix Coefficient 21 [CMA21 : 37h : 0dh]
7 6 5 4 3 2 1 0
Color Matrix Coefficient 21 0 0 0 0 1 1 0 1
Color Matrix Coefficient 22 [CMA22 : 38h : 3ch]
7 6 5 4 3 2 1 0
Color Matrix Coefficient 22 0 0 1 1 1 1 0 0
Color Matrix Coefficient 23 [CMA23 : 39h : f7h]
7 6 5 4 3 2 1 0
Color Matrix Coefficient 23 1 1 1 1 0 1 1 1
Color Matrix Coefficient 31 [CMA31 : 3ah : f8h]
7 6 5 4 3 2 1 0
Color Matrix Coefficient 31 1 1 1 1 1 0 0 0
Color Matrix Coefficient 32 [CMA32 : 3bh : cfh]
7 6 5 4 3 2 1 0
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Color Matrix Coefficient 32 1 1 0 0 1 1 1 1
Color Matrix Coefficient 33 [CMA33 : 3ch : 39h]
7 6 5 4 3 2 1 0
Color Matrix Coefficient 33 0 0 1 1 1 0 0 1
Gamma Segment Start Points Gamma Segment Start Points specify the start points of nine line segments for piecewise gamma approximation. Current default gamma curve is very selected for optimum gray gradation.
Gamma Point 0 [GAMP0 : 40h : 00h]
7 6 5 4 3 2 1 0
Gamma Point 0 0 0 0 0 0 0 0 0
Gamma Point 1 [GMAP1 : 41h : 04h]
7 6 5 4 3 2 1 0
Gamma Point 1 0 0 0 0 0 1 0 0
Gamma Point 2 [GMAP2 : 42h : 1ch]
7 6 5 4 3 2 1 0
Gamma Point 2 0 0 0 1 1 1 0 0
Gamma Point 3 [GMAP3 : 43h : 34h]
7 6 5 4 3 2 1 0
Gamma Point 3 0 0 1 1 0 1 0 0
Gamma Point 4 [GMAP4 : 44h : 54h]
7 6 5 4 3 2 1 0
Gamma Point 4
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0
1
0
1
0
1
0
0
Gamma Point 5 [GMAP5 : 45h : 78h]
7 6 5 4 3 2 1 0
Gamma Point 5 0 1 1 1 1 0 0 0
Gamma Point 6 [GMAP6 : 46h : 90h]
7 6 5 4 3 2 1 0
Gamma Point 6 1 0 0 1 0 0 0 0
Gamma Point 7 [GMAP7 : 47h : a4h]
7 6 5 4 3 2 1 0
Gamma Point 7 1 01 0 0 1 0 0
Gamma Point 8 [GMAP8 : 48h : e0h]
7 6 5 4 3 2 1 0
Gamma Point 8 1 1 1 0 0 0 0 0
Gamma Point 9 [GMAP9 : 49h : f4h]
7 6 5 4 3 2 1 0
Gamma Point 9 1 1 1 1 0 1 0 0
Gamma Slope Values Gamma Slope Registers are programmed as the integer value of real slope value that is multiplied by 64.
Gamma Slope 0 [GMAS0 : 50h : 40h]
7 6 5 4 3 2 1 0
Gamma Slope 0 0 1 0 0 0 0 0 0
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Gamma Slope 1 [GMAS1 : 51h : 80h]
7 6 5 4 3 2 1 0
Gamma Slope 1 1 0 0 0 0 0 0 0
Gamma Slope 2 [GMAS2 : 52h : 60h]
7 6 5 4 3 2 1 0
Gamma Slope 1 0 1 1 0 0 0 0 0
Gamma Slope 3 [GMAS3 : 53h : 40h]
7 6 5 4 3 2 1 0
Gamma Slope 3 0 1 0 0 0 0 0 0
Gamma Slope 4 [GMAS4 : 54h : 24h]
7 6 5 4 3 2 1 0
Gamma Slope 4 0 0 1 0 0 1 0 0
Gamma Slope 5 [GMAS5 : 55h : 18h]
7 6 5 4 3 2 1 0
Gamma Slope 5 0 0 0 1 1 0 0 0
Gamma Slope 6 [GMAS6 : 56h : 14h]
7 6 5 4 3 2 1 0
Gamma Slope 6 0 0 0 1 0 1 0 0
Gamma Slope 7 [GMAS7 : 57h : 0fh]
7 6 5 4 3 2 1 0
Gamma Slope 7 0 0 0 0 1 1 1 1
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Gamma Slope 8 [GMAS8 : 58h : 05h]
7 6 5 4 3 2 1 0
Gamma Slope 8 0 0 0 0 0 1 0 1
Gamma Slope 9 [GMAS9 : 59h : 02h]
7 6 5 4 3 2 1 0
Gamma Slope 9 0 0 0 0 0 0 1 0
Auto Exposure
Y mean value is continuously calculated every frame, and the integration time value is increased or decreased according to the displacement between current frame Y mean value and target Y mean value.
FFh
A E U n lo ck B o u n d a ry [6 8 h ]
A E L o ck B o u n d a ry [6 7 h ] 70h A E Ta rg e t [6 6 h] A E L o ck B o u n d a ry [6 7 h ]
A E U n lo ck B o u n d a ry [6 8 h ]
0h Y F ram e M e a n
AE Mode Control 1 [AEM1 : 60h : 39h]
7 6 5 4 3 2 1 0
Anti - Banding Enable
Full Window
Window Mode
AE speed
AE Mode
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0
0
1
1
1
0
0
1
Anti-Banding Enable
When
Anti-Banding
is
enabled,
AE
initializes
Integration
Time
registers[63h-65h] to 4 x Anti-Banding Step value[6ah-6ch], and integration increment/decrement amount is set to Anti-Banding Step value in order to remove banding noise caused by intrinsic energy waveform of light sources. Banding noise is inherent in CMOS image sensor that adopts rolling shutter scheme for image acquisition. In this mode, AE operates with very large unit, typically a reciprocal of (2 x power line frequency), so that minute integration time tuning is not liable. Therefore, this mode is recommended for only indoor use. Full Window With this bit set to high, window mode is discarded and full image data is accounted for AE Y frame mean evaluation Window Mode 11 1/8 center weighted window mode. Weighting ratio is 8:1 for inside area vs. outside area 10 01 1/8 center only window mode. 1/4 center weighted window mode. Weighting ratio is 4:1 for inside area vs. outside area 00 AE Speed AE Mode 1/4 center only window mode.
(fast)11 - 10 - 01 - 00(slow) 11 Gain-Only control mode. Only preamp gain is controlled to get optimum exposure state. 10 Time-Only control mode. Only integration time is controlled to get optimum exposure state. 01 Time-Gain control mode. integration time and preamp gain are controlled to get optimum exposure state. 00 AE function is disabled
AE Mode Control 2 [AEM2 : 61h : bah]
7 6 5 4 3 2 1 0
Gain Speed
Integration Time Fine Tune
Preamp Gain Fine Tune
AntiBanding Minimum Break
AE Subsampling mode
AE Analog Gain Control
AE Digital Gain control
1
0
1
1
1
0
1
0
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Gain Speed
Gain update speed is specified as follows. (fast)11 - 10 - 01 - 00(slow)
Integration Time Fine Tune Preamp Gain Fine Tune Anti-Banding Minimum Break
Integration time fine tuning is performed when AE arrive around AE Fine Tune Boundary to settle into AE lock state smoothly. Preamp gain fine tuning is performed when AE arrive around AE Fine Tune Boundary to settle into AE lock state smoothly. When AE is still of out lock state despite that AE preamp analog gain update value exceeds preamp minimum gain value(18h) and integration time(63h-65h) is reached to AE Anti-Banding Step(6ah-6ch), integration time(63h-65h) is broken to less than AE Anti-Banding Step(6ah-6ch).
AE Subsampling Mode AE Analog Gain Control AE Digital Gain Control
AE statistics is executed on 1/4 of original image data to save power consumption AE updates preamp gain register(17h) in order to reach optimum exposure state AE updates Y digital gain register(78h) in order to reach optimum exposure state
Integration Time High [INTH: 63h : 07h]
7 6 5 4 3 2 1 0
Integration Time High [23:16] 0 0 0 0 0 1 1 1
Integration Time Middle [INTM: 64h: a1h]
7 6 5 4 3 2 1 0
Integration Time Middle[15:8] 1 0 1 0 0 0 0 1
Integration Time Low [INTL: 65h: 20h]
7 6 5 4 3 2 1 0
Integration Time Low[7:0] 0 0 1 0 0 0 0 0
Integration time value register defines the time during which active pixel element evaluates photon energy that is converted to digital data output by internal ADC processing. Integration time is equivalent to exposure time of general camera so that integration time need to be increased in dark environment
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and decreased according to lighting condition. Maximum integration time is register maximum value(224-1) x sensor clock period(80ns, SCF 12.5Mhz @ DCF 25Mhz) = 1.34sec.
AE Target [AETGT : 66h : 70h]
7 6 5 4 3 2 1 0
AE Target 0 1 1 1 0 0 0 0
This register defines the target luminance value for AE operation.
AE Lock Boundary [AELBND : 67h : a2h]
7 6 5 4 3 2 1 0
AE Fine Boundary 1 0 1 0 0
AE Lock Boundary 0 1 0
AE Lock Boundary specifies the displacement of Y Frame Mean value(7dh) from AE Target in which AE goes into LOCK state. With Anti-Banding is enabled, this displacement condition is discarded, and instead AE Unlock Boundary is used as Lock boundary.
AE Fine Boundary specifies the displacement of Y Frame Mean value(7dh) from AE Target in which AE start to tune fine integration time or preamp gain in order to goes into lock state smoothly.
AE Unlock Boundary [AEUNLCK : 68h : 2ah]
7 6 5 4 3 2 1 0
AE Unlock Boundary 0 0 1 0 1 0 1 0
AE Unlock Boundary 0 specifies Y Frame Mean displacement from AE Target where integration time increment/decrement speed changes from 2x (integration unit step) to 1x (integration unit step). In antibanding mode, this boundary is used as lock boundary for exposure control.
AE Anti-Banding Step High [AEANTH : 6ah : 1h]
7 6 5 4 3 2 1 0
reserved 0 0 0 0 0 0
AE Anti-Banding Step High
0
1
AE Anti-Banding Step Middle [AEANTM : 6bh : e8h]
7 6 5 4 3 2 1 0
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AE Anti-Banding Step High 1 1 1 0 1 0 0 0
AE Anti-Banding Step Low [AEANTL : 6ch : 48h]
7 6 5 4 3 2 1 0
AE Anti-Banding Step Low 0 1 0 0 1 0 0 0
AE Anti-Banding Step specifies integration time unit value that AE uses when Anti-Banding is enabled. Anti-Banding Step value is resolved by the following equation. Anti-Banding Step Value = Sensor Operation Frequency (SCF) / (2x power line frequency) The default value is set with SCF 12.5Mhz, 50Hz power line, that is, Anti-Banding Step Value = 12.5Mhz / (2 x 50) = 125000d = 1e848h
AE Integration Time Limit High [AELMH : 6dh : 17h]
7 6 5 4 3 2 1 0
AE Integration Time Limit High 0 0 0 1 0 1 1 1
AE Integration Time Limit Middle [AELMM : 6eh : d7h]
7 6 5 4 3 2 1 0
AE Integration Time Limit Middle 1 1 0 1 0 1 1 1
AE Integration Time Limit Low [AELML : 6fh : 84h]
7 6 5 4 3 2 1 0
AE Integration Time Limit Low 1 0 0 0 0 1 0 0
These three registers define the maximum integration time value that is allowed to sensor operation. It is desirable to set the value to multiples of AE Anti-Banding Step to easily operate with Anti-banding mode enabled. The default value is set to 1/8sec with SCF set to 25Mhz 12.5Mhz / 8 = 1,562,500 = 17d784
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Auto White Balance
Cb/Cr frame mean value is calculated every frame and according to Cb/Cr frame mean values' displacement from Cb/Cr white target point, R/B scaling values for R/B data are resolved.
FFh A W B W h ite P ix e l B o u n d a r y [ 7 7 h
A W B U n lo c k B o u n d a r y [7 6 h ]
A W B L o c k B o u n d a r y [7 5 h ] 80h C b / C r Ta r g e t [7 3 h - 7 4 h ] A W B L o c k B o u n d a r y [7 5 h ]
A W B U n lo c k B o u n d a r y [7 6 h ]
A W B W h it e P ix e l B o u n d a r y [7 7 h 0h C b /C r F r a m e M e a n
AWB Mode Control 1 [AWBM : 70h : 41h]
7 6 5 4 3 2 1 0
reserved
Full Window
Window Mode
AWB speed
reserved
AWB On
0
1
0
0
0
0
0
1
Full Window
With this bit set to high, window mode is discarded and full image data is accounted for AE Y frame mean evaluation
Window Mode
11
1/8 center weighted window mode. Weighting ratio is 8:1 for inside area vs. outside area
10 01
1/8 center only window mode. 1/4 center weighted window mode. Weighting ratio is 4:1 for inside area vs. outside area
00
1/4 center only window mode.
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AWB Speed AWB On
(Fast)11 - 10 - 01 - 00(slow) Auto White Balance Control Enabled
AWB Mode Control 2 [AEM2 : 71h : 02h]
7 6 5 4 3 2 1 0
Reserved
AWB Low Speed
AWB Subsampling mode
AWB Analog Gain Control
AWB Digital Gain control
0
0
0
0
0
0
1
0
AWB Low Speed
With this bit set to high, analog gain speed is decreased to 1/4 of the normal speed.
AWB Subsampling Mode AWB Analog Gain Control AWB Digital Gain Control
AWB statistics is executed on 1/4 of original image data to save power consumption AWB updates R/B gain registers(14h,16h) in order to reach optimum white balance state AWB updates Cb/Cr digital gain registers(79h,7ah) in order to reach optimum white balance state
Cb Target [CBTGT : 73h : 80h]
7 6 5 4 3 2 1 0
Cb Target 1 0 0 0 0 0 0 0
This register defines Cb target frame mean value for AWB operation.
Cr Target [CRTGT : 74h : 80h]
7 6 5 4 3 2 1 0
Cr Target 1 0 0 0 0 0 0 0
This register defines Cr target frame mean value for AWB operation.
AWB Lock Boundary [AWBLB : 75h : 2h]
7 6 5 4 3 2 1 0
Reserved
AWB Lock Boundary
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0
0
0
0
0
0
1
0
It specifies Cb/Cr frame mean values' displacement from Cb/Cr Target (73h-74h) value where AWB goes into LOCK state.
AWB Unlock Boundary [AWBUB : 76h : 06h]
7 6 5 4 3 2 1 0
AWB Unlock Boundary 0 0 0 0 0 1 1 0
It specifies Cb/Cr frame mean values' displacement from Cb/Cr Target (73h-74h) where AWB is released from LOCK state. AWB operation retains LOCK state unless Cb/Cr frame mean values' displacement value exceeds this boundary. The value should be larger AWB Lock Boundary.
AWB White Pixel Boundary [AWBWPB : 77h : 30h]
7 6 5 4 3 2 1 0
AWB White Pixel Boundary 0 0 1 1 0 0 0 0
When Cb/Cr frame mean values' displacement from Cb/Cr Target exceeds AWB White Pixel Boundary value, AWB accept frame color as it is and does not try to correct white balance deviation.
Y Digital Gain [YGAIN : 78h : 40h]
7 6 5 4 3 2 1 0
Y Digital Gain 0 1 0 0 0 0 0 0
The register represents the current Y digital gain value (1/64 resolution) in Digital Gain block, and is updated every frame by AE logic when AE digital gain update mode is active.
Cb Digital Gain [CBGAIN : 79h : 40]
7 6 5 4 3 2 1 0
Cb Digital Gain 0 1 0 0 0 0 0 0
The register represents the current Cb digital gain value (1/64 resolution) in Digital Gain block, and is updated every frame by AWB logic when AWB digital gain update mode is active.
Cr Digital Gain [AWBSCLB : 7ah : 40h]
7 6 5 4 3 2 1 0
Cr Digital Gain
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0
1
0
0
0
0
0
0
The register represents the current Cr scaling value(1/64 resolution) in Digital Gain block, and is updated every frame by AWB logic when AWB digital gain update mode is active.
AE Status [AEST : 7bh : RO]
7 6 5 4 3 2 1 0
AE Mode State
RO RO RO RO RO
AE Lock state
RO RO RO
AE State
Mode This nibble represents the mode where internal Y plane FSM is currently placed among time-gain control, time-only control, or gain-only control modes. Y channel FSM status, "0000" means that AE Y plane is in lock state
AE Lock State
AWB Status [AWBST : 7ch : RO]
7 6 5 4 3 2 1 0
Reserved
AE/AWB Lock
Cb Lock State
Cr Lock State
RO
RO
RO
RO
RO
RO
RO
RO
AE/AWB Lock
This single status bit indicates that AE and AWB are in lock state for optimum still image capture.
Cb Lock State Cr Lock State
Cb channel FSM status. "00" means that AWB Cb plane is in lock state Cr channel FSM status. "00" means that AWB Cr plane is in lock state
Y Frame Mean [YFMEAN : 7dh : RO]
7 6 5 4 3 2 1 0
Y Frame Mean
RO RO RO RO RO RO RO RO
The register reports current Y plane frame mean value.
Cb Frame Mean [CBFMEAN : 7eh : RO]
7 6 5 4 3 2 1 0
Cb Frame Mean
RO RO RO RO RO RO RO RO
The register reports current Cb plane frame mean value.
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Cr Frame Mean [CRFMEAN : 7fh : RO]
7 6 5 4 3 2 1 0
Cr Frame Mean
RO RO RO RO RO RO RO RO
The register reports current Cr plane frame mean value.
Minimum Anti-Banding Gain [BNDGMIN : 80h : 08h]
7 6 5 4 3 2 1 0
Minimum Anti-Banding Gain 0 0 0 0 1 0 0 0
The register specifies the minimum limit to which AE may decrease preamp gain or Y digital gain in order to get optimum exposure value while Anti-Banding Mode is enabled and the following condition is met. AE Lock Boundary < (Y Frame Mean - AE Target) < AE Unlock Boundary.
Maximum Anti-Banding Gain [BNDGMAX : 81h : 18h]
7 6 5 4 3 2 1 0
Maximum Anti-Banding Gain 0 0 0 1 1 0 0 0
The register specifies the maximum limit to which AE may increase preamp gain or Y digital gain in order to get optimum exposure value while Anti-Banding Mode is enabled and the following condition is met. AE Lock Boundary < (AE Target - Y Frame Mean) < AE Unlock Boundary.
Integration-Scan Offset High [ISOFSH : 82h : RO]
7 6 5 4 3 2 1 0
Integration-Scan Offset High
RO RO RO RO RO RO RO RO
Integration-Scan Offset Middle [ISOFSM : 83h : RO]
7 6 5 4 3 2 1 0
Integration-Scan Offset Middle
RO RO RO RO RO RO RO RO
Integration-Scan Offset Low [ISOFSH : 84h : RO]
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7
6
5
4
3
2
1
0
Integration-Scan Offset Low
RO RO RO RO RO RO RO RO
The register represents time offset between integration plane and scan plane. The value should be the same as the value specified by integration time register(63h - 65h).
AWB Luminance High Boundary [AWBLUHI : 8ah : c8h]
7 6 5 4 3 2 1 0
AWB Luminance High Boundary 1 1 0 0 1 0 0 0
During Cb/Cr frame mean value calculation, AWB discards pixel of which luminance value is larger than this register value.
AWB Luminance Low Boundary [AWBLULO : 8bh : 0ah]
7 6 5 4 3 2 1 0
AWB Luminance Low Boundary 0 0 0 0 1 0 1 0
During Cb/Cr frame mean value calculation, AWB discards pixel of which luminance value is smaller than this register value.
AWB Valid Number [AWBNO : 8ch : 02h]
7 6 5 4 3 2 1 0
AWB Valid Number 0 0 0 0 0 0 1 0
AWB update when the number of valid color pixel is larger than (this valid value x 64).
Dark Bad Pixel Concealment Mode [DPCMODE : 90h : 0h]
7 6 5 4 3 2 1 0
Reserved
Dark Bad Pixel Concealment Mode
0
0
0
0
0
0
0
0
Dark Bad Pixel Concealment 10
Dark Bad Pixel Concealment is always performed.
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Mode
01
Dark Bad Pixel Concealment is performed when Integration Time (63h-65h) exceeds Dark Bad
Integration Time(91h-93h) 11, 00 Dark Bad Pixel Concealment is turned off
Dark Bad Integration Time High [DPCINTH : 91h : 13h]
7 6 5 4 3 2 1 0
Dark Bad Integration Time High 0 0 0 1 0 0 1 1
Dark Bad Integration Time Middle [DPCINTM : 92h : 12h]
7 6 5 4 3 2 1 0
Dark Bad Integration Time Middle 0 0 0 1 0 0 1 0
Dark Bad Integration Time Low [DPCINTL : 93h : d0h]
7 6 5 4 3 2 1 0
Dark Bad Integration Time Low 1 1 0 1 0 0 0 0
Dark Bad Integration Time registers(91h-93h) specify minimum integration time value(63h-65h) where dark bad concealment operation is performed when dark bad pixel concealment mode is "01 (binary)".
Dark Bad G Threshold [DPCGTH : 94h : 0ch]
7 6 5 4 3 2 1 0
Dark Bad G Threshold 0 0 0 0 1 1 0 0
The register value specify the current G pixel's differential value with neighboring G pixels, and is used to check whether current G pixel is dark bad pixel or not.
Dark Bad C Threshold [DPCGTH : 95h : 0ch]
7 6 5 4 3 2 1 0
Dark Bad C Threshold 0 0 0 0 1 1 0 0
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The register value specify the current R or B pixel's differential value with neighboring G pixels, and is used to check whether current R or B pixel is dark bad pixel or not.
Frame Timing
For clear description of frame timing, clocks' acronym and relation are reminded in here again.
< Clock Acronym Definition > MCF : Master Clock Frequency SCF : Sensor Clock Frequency VCF : Video Clock Frequency DCF : Divided Clock Frequency ICF : Image Processing Clock Frequency LCF : Line Clock Frequency
< Clock Frequency Relation > MCF : MCF SCF : DCF/2 DCF : MCF/Clock Division ICF SCF for 3x3 interpolation,
SCF/2 for 1/4 subsampling mode SCF/4 for 1/16 subsampling mode VCF : ICF for 16bit output, ICF*2 for 8bit output LCF : 1/(HBLANK Period + HSYNC Period)
HBLANK Period : HBLANK Time register value * (1/SCF) HSYNC Period : HSYNC Active Time
< Frame Time Calculation > Core Frame Time is (IDLE SLOT + Video Height * LCP) and Real Frame Time is resolved as follows. When Integration Time > Core Frame Time, Real Frame Time is (Integration Time + VBLANK * LCP), otherwise is (Core Frame Time + VBLANK * LCP). 1. 3x3 Color Interpolation Timing
3x3 Color Interpolation Frame Timing Related Parameters
Master Clock Frequency(MCF) Sensor Clock Frequency(SCF) Window Width HBLANK Value VSYNC Mode Output Bus Width 20Mhz DCF/2 = 10Mhz 640 208 Line Mode 8bit Divided Clock Frequency(DCF) Sensor Clock Period(SCP) Window Height VBLANK Value Line Clock Period(LCP) VGA Video Output Frequency MCF/1 = 20Mhz 1/10Mhz = 100ns 480 8 848 SCPs SCF * 2 = 20Mhz
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Final Video Output Size
640x480
.
.
If Integration Time < Core Frame Time, Real Frame Time is 2 * (208 + 640) SCPs + 480 * (208 + 640) SCPs + 8 * (208 + 640) SCPs = 415520 SCPs = 0.041552sec else Real Frame Time is Integration Time * SCPs + 8 * (208 + 640) SCPs.
HOLD SLOT in frame timing appears only if integration time is larger than core frame time.
IDLE SLOT(2LCPs + (512+HBLANK)*4)
Core Frame Time
HBLANK (208 SCPs)
HSYNC (640 SCPs) Active Data: 640 EA
Video Lines is active every LCP, that is, 480 Video Lines
LCP(848 SCPs)
for 480 LCPs
HOLD SLOT (Integration Time - Core Frame Time) VBLANK[VSYNC] (8 LCPs) Real Frame Time
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One active Video Line is equal to one Line Clock Period(LCP) = 848 SCPs SCF (10Mhz)
HBLANK (208 SCPs)
HSYNC (640 SCPs)
VCF[VCLK] (20Mhz)
Y[7:0]
Y
Cb
Y
Cr
Y
Cb
Y
Cr
2. 1/4 Subsampling Timing
1/4 Subsampling Frame Timing Related Parameters
Master Clock Frequency(MCF) Sensor Clock Frequency(SCF) Window Width HBLANK Value VSYNC Mode Output Bus Width Final Video Output Size 20Mhz DCF/2 = 10Mhz 640 208 Line Mode 8bit 320x240 Divided Clock Frequency(DCF) Sensor Clock Period(SCP) Window Height VBLANK Value Line Clock Period(LCP) SIF Video Output Frequency MCF/1 = 20Mhz 1/10Mhz = 100ns 480 8 848 * 2 SCPs SCF * 1 = 10Mhz
In 1/4 subsampling mode, valid video data is produced every other line, i.e. for 480 LCPs, active video lines are 240. HSYNC active time is equal to HSYNC active time of 3x3 color interpolation mode, but video clock frequency is half of 3x3 color interpolation mode's to produce half size output in horizontal direction.
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IDLE SLOT ((512+HBLANK)*4)
Core Frame Time
1 IDLE LINE (848SCPs)
Video Lines is active every other LCP, that is,
HBLANK (208 SCPs)
HSYNC (640 SCPs) Active Data: 320 EA
240 Video Lines for 480 LCPs
HOLD SLOT (Integration Time - Core Frame Time) VBLANK[VSYNC] (8 LCPs) Real Frame Time
One active Video Line is equal to two Line Clock Period(LCP) = (848 x 2) SCPs HBLANK (208 SCPs)
1 IDLE LINE (848 SCPs)
HSYNC (640 SCPs)
SCF (10Mhz)
VCF[VCLK] (10Mhz)
Y[7:0]
Y
Cb
Y
Cr
3. 1/16 Subsampling Timing
1/16 Subsampling Frame Timing Related Parameters
Master Clock Frequency(MCF) Sensor Clock Frequency(SCF) 20Mhz DCF/2 = 10Mhz Divided Clock Frequency(DCF) Sensor Clock Period(SCP) MCF/1 = 20Mhz 1/10Mhz = 100ns
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Window Width HBLANK Value VSYNC Mode Output Bus Width Final Video Output Size
640 208 Line Mode 8bit 160x120
Window Height VBLANK Value Line Clock Period(LCP) QSIF Video Output Frequency
480 8 848 * 4 SCPs SCF / 2 = 5Mhz
In 1/16 subsampling mode, valid video data is produced every four line, i.e. for 480 LCPs, active video lines are 120. HSYNC active time is equal to HSYNC active time of 3x3 color interpolation mode, but video clock frequency is a quarter of 3x3 color interpolation mode's to produce a quarter size output in horizontal direction.
Core Frame
IDLE SLOT ( (512+HBLANK)*4)
Time
Video data is active at last 1 LCP
3 IDLE LINES (3 * 848 SCPs)
period of every 4 LCPs period, that is,
HBLANK (208 SCPs)
HSYNC (640 SCPs) Active Data: 160 EA HOLD SLOT (Integration Time - Core Frame Time) VBLANK[VSYNC] (8 LCPs)
120 Video Lines for 480 LCPs
Real Frame Time
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One active Video Line is equal to four Line Clock Period(LCP) = 848 x 4 SCPs HBLANK (208 SCPs)
3 IDLE LINES (3 * 848 SCPs)
HSYNC (640 SCPs)
SCF (10Mhz)
VCF[VCLK] (5Mhz)
Y[7:0]
Y
Cb
Anti-Banding Configuration
For Anti-Banding mode to work correctly, the following registers should be configured to the appropriate values.
AE Mode AE Anti-Banding Step AE Integration Time Limit
60h 6a-6ch 6d-6fh
Anti-Banding Enable[7] SCF / (2 x power line frequency) The value should be multiples of AE Anti-Banding Step
When Anti-Banding is enabled, AE initializes Integration Time registers[63-65h] to 4 x Anti-Banding Step value[6a-6ch], and integration increment/decrement amount is set to Anti-Banding Step value in order to remove anti-banding noise caused by intrinsic energy waveform of light sources. Banding noise is inherent in CMOS image sensor that adopts rolling shutter scheme for image acquisition.
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Data Output Timing and Interface
14ns ~ 15ns M C LK
V C LK
HSYNC
Y [7 :0 ]
X
Y0
Y1
Y2
C [7 :0 ]
X
Cb0
C r0
C b1
4ns ~ 5ns
As specified in the above data output timing diagram, the timing margin between video clock pin (VCLK) and data pins (Y[7:0] or C[7:0]) is about 4ns ~ 5ns. This margin may be sufficient or not according to how much video clock and data pins are delayed internally in the backend chip, respectively. To safely latch the data output in the backend chip, it is recommended that data be latched at negative edge of VCLK. The above timing margin diagram represents 16bit output interface, but is also valid for 8bit output interface.
Output Data Format
Output Format is controlled by configuring Output Format register[31h]. Configurable options are specified again for your reference.
Output Format [OUTFMT : 31h : 39h]
7 6 5 4 3 2 1 0
reserved
reserved
Cb First
Y First
8 Bit Output
reserved
YCbCr 4:4:4
YCbCr 4:2:2
0
0
1
1
1
0
0
1
Cb First Y First
Cb pixel in front of Cr pixel in 16bit or 8bit video data output modes Y pixel in front of Cb and Cr pixels in 8bit video output mode. This option is meaningful only with 8bit output mode.
8 Bit Output
Image Data is produced only in Y[7:0]. C[7:0] should be discarded
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YCbCr 4:4:4
YCbCr 24bit data for a pixel is produced with 16bit output mode. With color space conversion disabled, RGB 24bit data for a pixel is produced in this mode. This mode is meaningful only with 16bit output mode.
YCbCr 4:2:2
YCbCr data for a pixel is produced with 8/16 output mode
Output timings for general configurations are described below. Slot named as "X" means that it is has no meaningful value and should be discarded.
1. YCbCr 4:2:2 with 16bit output Register bit configurations: 16bit output, Cb First, YCbCr 4:2:2
VCLK
HSYNC
Y[7:0]
X
Y0
Y1
Y2
Y3
Y4
Y5
C[7:0]
X
Cb0
Cr0
Cb1
Cr1
Cb2
Cr2
2. YCbCr 4:2:2 with 8bit output Register bit configurations: 8bit output, Y First, Cb First, YCbCr 4:2:2
VCLK
HSYNC
Y[7:0]
X
X
Y0
Cb0
Y1
Cr0
Y2
Cb1
Y3
Cr1
Y4
Cb2
Y5
Cr2
C[7:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
3. 24bit YCbCr 4:4:4 output Register bit configurations : 8bit output, Y First, Cb First, YCbCr 4:4:4, and color space conversion enabled
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VCLK
HSYNC
Y[7:0]
X
X
Y0
X
Y1
X
Y2
X
Y3
X
Y4
X
Y5
X
C[7:0]
X
X
Cb0
Cr0
Cb1
Cr1
Cb2
Cr2
Cb3
Cr3
Cb4
Cr4
Cb5
Cr5
4. 24bit RGB 4:4:4 output Register bit configurations : 8bit output, Y First, Cb First, YCbCr 4:4:4, and color space conversion disabled
VCLK
HSYNC
Y[7:0]
X
X
G0
X
G1
X
G2
X
G3
X
G4
X
G5
X
C[7:0]
X
X
B0
R0
B1
R1
B2
R2
B3
R3
B4
R4
B5
R5
Bayer Data Format
SCTRA[1:0] is set to Bayer mode - When Bayer output mode is selected, Window Width x Window Height raw image data are produced with the following sequence. After VSYNC goes low state, the first HSYNC line of a frame is activated with B pixel data appearing first when both of Column Start Address and Row Start Address are even.
VCLK
HSYNC
Y[7:0] Even Line Y[7:0] Odd Line
X
B
G
B
G
B
G
X
G
R
G
R
G
R
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I2C Chip Interface
Register Write Sequences
One Byte Write
S *1
22H *2
A *3
01H *4
A *5
03H *6
A *7
P *8
Set "Sensor Control A" register into Window mode *1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit] *3. Read: acknowledge from sensor *4. Drive: 01H [sub-address] *5. Read: acknowledge from sensor *6. Drive: 03H [Video Mode : CIF *7. Read: acknowledge from sensor *8. Drive: I2C stop condition
Multiple Byte Write using Auto Address Increment
S *1
22H *2
A *3
6aH *4
A *5
51H *6
A *7
61H *8
A *9
P *10
Set "AE Integration Step High/Low" register as 5161H with auto address increment *1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit] *3. Read: acknowledge from sensor *4. Drive: 6aH [sub-address] *5. Read: acknowledge from sensor *6. Drive: 51H [AE Integration Step High] *7. Read: acknowledge from sensor *8. Drive: 61H [AE Integration Step Low] *9. Read: acknowledge from sensor *10. Drive: I2C stop condition
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Register Read Sequence
S
*1
22H
*2
A
*3
50H
*4
A
*5
S
*6
23H
*7
A
*8
Data of 50H
*9
A
P
*10 *11
Read "Reset Level Control" register from HV7131GP *1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit(be careful. R/W=0)] *3. Read: acknowledge from sensor *4. Drive: 50H [sub-address] *5. Read: acknowledge from sensor *6. Drive: I2C start condition *7. Drive: 23H(001_0001 + 1) [device address + R/W bit(be careful. R/W=1)] *8. Read: acknowledge from sensor *9. Read: Read "Reset Level Control Value" from sensor *10. Drive: acknowledge to sensor. If there is more data bytes to read, SDA should be driven to low and data read states(*9, *10) is repeated. Otherwise SDA should be driven to high to prepare for the read transaction end. *11. Drive: I2C stop condition
AC/DC Characteristics
Absolute Maximum Ratings
Symbol Parameter Units Min. Max.
Vdpp Vapp Vipp Top Tst
Digital supply voltage Analog supply voltage Input signal voltage Operating Temperature Storage Temperature
Volts Volts Volts
C C
-0.3 -0.3 -0.3 -30 -40
7.0 7.0 7.0 70 85
Caution: Stresses exceeding the absolute maximum ratings may induce failure.
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DC Characteristic
Symbol Parameter Units Min. Typical. Max. Conditions&Note
Vdd Idd HsIdd SsIdd Vih Vil Voh Vol Iih Iil Ta Cin Cout Cbid
Internal operation supply voltage Operating current consumption Hard Sleep Static current consumption Soft Sleep Static current consumption Input voltage logic "1" Input voltage logic "0" Output voltage logic "1" Output voltage logic "0" Input High Current Input Low Current Ambient operating temperature Input capacitance Output capacitance Bi-directional buffer capacitance
Volt mA uA uA Volt Volt Volt Volt uA uA Celsiu s pF pF pF
2.6
-
3.0 40 48 276 3.0 0.8 0.4 10 10 50 30 30
At 15fps(12.5Mhz) At 15fps(12.5Mhz)
At 15fps(12.5Mhz)
2.0 0 2 -10 -10 -10 5 -
-
at Ioh = -4mA at Iol = 4mA -
Epud
R Epud External pull-up / pull-down resistance Ohm Note.1) R Epud is just applied to SDA and SCK pin. And If R consumption is increased.
20k 1) is less than 20K Ohm, power
AC Operating Conditions
Symbol Parameter Max Operation Frequency Units Notes
MCLK SCK
Main clock frequency I2C clock frequency
25 400
MHz KHz
1,2 3
1. MCLK may be divided by internal clock division logic for easy integration with high speed video codec system. 2. Frame Rate : 30 frames/sec at 25Mhz, HBLANK = 208, VBLANK = 8 3. SCK is driven by host processor. For the detail serial bus timing, refer to I2C chip interface section
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Output AC Characteristics
All output timing delays are measured with output load 60[pF]. Output delay includes the internal clock path delay and output driving delay that changes in respect to the output load, the operating environment, and a board design. Due to the variable valid time delay of the output, video output signals Y[7:0], C[7:0], HSYNC, and VSYNC may be latched in the negative edge of VCLK for the stable data transfer between the image sensor and video codec.
V C LK
HSYNC
Y /C [7:0]
X
D ata 0
D ata 1
D ata 2
D ata 3
4ns ~ 5ns
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I2C Bus Timing
stop
start
start
stop
SDA
tr tbuf tlow tf thd;sta
SCK
thd;sta
thd;dat
thigh
tsu;dat
tsu;sta
tsu;sto
Parameter
Symbol
Min.
Max.
Unit
SCK clock frequency Time that I2C bus must be free before a new transmission can start Hold time for a START LOW period of SCK HIGH period of SCK Setup time for START Data hold time Data setup time Rise time of both SDA and SCK Fall time of both SDA and SCK Setup time for STOP Capacitive load of SCK/SDA
fsck tbuf thd;sta tlow thigh tsu;sta thd;dat tsu;dat tr tf tsu;sto Cb
0 1.2 1.0 1.2 1.0 1.05 0.1 250 1.05 -
400 250 300 30
KHz us us us us us us ns ns ns us pf
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Electro-Optical Characteristics
Parameter Units Min. Typical Max. Note
Sensitivity Dark Signal Output Saturation Signal
mV / lux sec mV mV
3000 12 1000
Green Pixel 1/10" , 60
- Color temperature of light source: 3200K / IR cut-off filter (CM-500S, 1mm thickness) is used.
Soldering
Infrared(IR) / Convection solder reflow condition
Parameter Units Min. Typical Max. Note
Peak Temperature Range Note:
Celsius
-
230
240
1)
1) Time within 5 Celsius of actual peak temperature, 10sec
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CLCC Package Specification
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* To the matter concerning package, Wafer business companies are unrelated contents.
MagnaChip Semiconductor Ltd.
* Contact Point *
CIS Marketing Team
891 Daechi-dong Kangnam-Gu Seoul 135-738 Korea Tel: 82-2-3459-5577 Fax: 82-2-3459-5580 E-mail : hanho1.lee@magnachip.com
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